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2-31 features ? st-bus/gci compatible switch matrix ? 64 channel non-blocking time switch ? 2 x 32 channel serial inputs and outputs ? per-channel tristate control ? 4-pin serial microprocessor interface ? patented message mode ? low power consumption (10 mw) ? single 5 volt supply applications ? cost sensitive digital switching applications ? digital key telephone systems ? gci/st-bus conversion ? st-bus device control interface ? isdn telephone set support circuit ? interprocessor communication description the MT8982 small digital switch (minidx) is a non- blocking cmos time switch with a capacity of up to 64 - 8 bit time division multiplexed (tdm) encoded voice or data channels. it is a size-optimized version of mitel's successful mt8980d digital switches, providing switching capability in cost sensitive applications such as telephone sets and digital key systems. the tdm interface to the device is via two pairs of 2048 kbit/s serial streams with 32 64 kbit/s channels per stream (st-bus). a serial microport provides access to the device for programming the required connections. the serial microport is compatible with most common microcontrollers. the unique message mode capability allows the MT8982 to act as a controller for other members of mitel's st-bus family of components. figure 1 - functional block diagram sti0 sti1 f0i c4i f0o rxd/csti0 txd/nc sclk/csti1 cs/cms mps ode sto0 sto1 serial to parallel converter 64 x 8 data memory output mux parallel to serial converter address mux address counters serial microport 64 x 9 connect memory address mux 3-state control data mux issue 6 may 1995 MT8982 small digital switch (minidx) iso-cmos st-bus ? family ordering information MT8982ae 16 pin plastic dip MT8982as 16 pin soic MT8982an 20 pin ssop -40 to +85 c
MT8982 iso-cmos 2-32 figure 2 - pin connections pin description pin # name description 16 20 1-2 1-2 sti0- sti1 serial tdm input 0 and 1 (inputs). 2048 kbit/s input data streams containing 32 8-bit channels synchronized to f0i. 3-4 4-5 sto0- sto1 serial tdm output 0 and 1 (outputs). 2048 kbit/s output data streams containing 32 8-bit channels synchronized to f0i. 5 6 rxd/ csti0 received data/control stream input 0 (input). when mps is low, this pin receives serial microport data clocked in by the rising edge sclk. when mps is high, this pin receives a 2048 kbit/s serial tdm stream containing 32 8-bit channels, which are written into the connect memory locations corresponding to sto0. 6 7 txd transmit data (output). when mps is low, serial microport data is clocked out on this pin by the falling edge of sclk. when mps is high this output is disabled. 7 9 sclk/ csti1 serial microport clock/control stream input 1 (input). when mps is low, this pin receives a clock which is used to clock data to/from a microcontroller via a serial microport. when mps is high, this pin receives a 2048 kbit/s serial tdm stream containing 32 8-bit channels, which are written into the connect memory locations corresponding to sto1. 810 v ss power input. negative supply (ground). 911 cs chip select (input). when mps is low, a low on this pin enables the serial microport. a high on this pin disables rxd and tristates txd. when mps is high, this pin must be low. 10 12 c4i serial tdm clock (input). this clock input is used to clock the tdm data into and out of the device and refreshes the internal dynamic ram. the clock rate is 4.096 mhz and data is clocked in on the rising edge of c4i three-quarters of the way through a bit period. 11 14 f0i frame pulse (input). this input is the frame synchronization pulse for the 2048 kbit/s serial tdm streams. it may be either active low stradling the frame boundary (st-bus) or active high at the beginning of timeslot 5 (gci). 12 16 f0o frame pulse (output). this pin outputs a frame pulse in the opposite format to f0i (gci or st-bus) delayed or advanced by ?ve channels. 13 17 mps microport select (input). when this pin is held low, the serial microport is in normal mode. when this pin is high, the microport is in serial bus mode. 14 18 ic internal connection. tie to v ss for normal operation. 15 19 ode output drive enable (input). when this pin is held high, the sto0 and sto1 output drivers function normally. when this pin is low, sto0 and sto1 are tristated. nb: when ode is high, individual channels on sto0 and sto1 can be tristated under software control. 16 20 v dd power input. positive supply. 3,8, 13,15 nc no connection. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 pin plastic/soic sti0 sti1 sto0 sto1 rxd/csti0 txd/nc sclk/csti1 vss vdd ode ic mps f0o f0i c4i cs 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 sti0 sti1 nc sto0 sto1 rxd/csti0 txd/nc nc sclk/csti1 vss 20 pin ssop vdd ode ic mps nc f0i nc c4i cs f0o
iso-cmos MT8982 2-33 functional description the MT8982 (minidx) provides cost effective time switching capability for small size applications utilizing up to two serial time division multiplexed (tdm) streams. each tdm stream consists of 32 64 kb/s channels, giving the minidx a maximum capacity of 64 channels. the input framing signal may be either a st-bus or a gci frame pulse. the MT8982 will output a delayed or advanced frame pulse in the opposite format to permit conversion between the two formats. the minidx can switch data from any channel in one of the two serial input tdm streams to any channel in either of the two serial output tdm streams. the microcontroller controlling the minidx writes to the MT8982 connect memory to establish the connection between the required input tdm channel and the selected output tdm channel(s). by reading the connect memory the microcontroller can check switched connections which have already been established. the minidx can also operate in message mode where the microcontroller transmits the data on the tdm serial stream. the microcontroller writes to the MT8982 connect memory to transmit data on the required output tdm channels. reading the data memory of the MT8982 allows the microcontroller to receive messages from tdm input channels. these operations are useful for control of other st-bus components or for interprocessor communication. hardware description tdm interface the MT8982 continuously receives tdm serial data at 2048 kbit/s through two serial inputs. these serial streams are then converted into a parallel format and stored sequentially in a 64x8 bit data memory. the sequential addressing is generated by an internal counter that is reset by the input 8 khz frame pulse ( f0i) which marks the frame boundaries of the incoming serial data stream. this counter increments with each timeslot so that it matches the binary count of the timeslot of the incoming data. the tdm timeslot count always corresponds to the st-bus channel positions. an extra address bit is used to differentiate between the two input data streams. the input 8 khz frame pulse may be either st-bus or gci formatted. a st-bus formatted frame pulse is an active low signal which straddles the frame boundary. it idles high the rest of the time. a gci formatted frame pulse is active high at the beginning of timeslot 5 (relative to the MT8982) and idles low. the MT8982 automatically determines the type of frame pulse from the level of the idle over ?ve clock periods. a st-bus formatted frame pulse resets the internal address counters to zero. a gci formatted frame pulse resets the counters to ?ve. f0o outputs a frame pulse in the opposite format. if f0i is a st-bus formatted frame pulse, f0o will be a gci formatted frame pulse delayed by ?ve channels after f0i. if f0i is a gci formatted frame pulse, f0o will be a st-bus formatted frame pulse delayed by 27 channels (32-5). during normal operation every second falling edge of the clock marks a timeslot boundary and the input data is clocked in by the rising edge, three-quarters of the way into the bit cell. the master clock must be 4.096 mhz for the f0o signal to be valid and to receive a gci formatted f0i. data which is output onto a tdm serial output channel may come from two sources; the data memory or the connect memory. if a channel is con?gured in connection mode, the source of output data is the data memory. if a channel is con?gured in message mode, the source of the output data is the connect memory. data destined for a particular channel on the serial output links is read from the data or connect memory in the previous channel timeslot. this allows for delay in ram access and parallel-to-serial conversion. each output data channel can also be placed in tristate mode. when an output channel is in connection mode, the tdm output data is read from a data memory location pointed to by an address stored in the 64x8 bit connect memory. the connect memory locations are addressed sequentially, with each location corresponding to an output tdm link/ channel. in the channel time before the data is to be output, the contents of each connect memory location are output to the address bus of the data memory. the contents of the data memory at the selected address are then transferred to the parallel- to-serial converter. the parallel-to-serial converter outputs onto the tdm serial stream during the correct channel time. by having the output channel specify the input channel, the user can route the same input channel to several output channels. this function is useful for broadcasting or resource channel uses.
MT8982 iso-cmos 2-34 when an output channel is in message mode, the data for the output channel originates from the microcontroller. the microcontroller writes data to the connect memory location which corresponds to the output link and channel number. the contents of the connect memory are transferred directly to the serial-to-parallel converter one channel time before it is to be output. the connect memory data is output msb ?rst, repetitively once per frame, until it is changed by the microcontroller. if the output channel is con?gured in tristate mode, the tdm serial stream output will be placed in high impedance during that channel time. this mode is entered by con?guring the channel into connection mode and then setting the tristate control bit. all channels on both output tdm streams can be tristated by pulling pin 16 (ode) low. this overrides the individual channel programming. the data and connect memories are dynamic memories. they are refreshed by the sequential addressing generated by c4i. microcontroller interface the MT8982 is controlled via a synchronous, serial microport. the microport is compatible with intel's mcs-51 serial port mode 0 speci?cations, motorola's serial peripheral interface (spi) speci?cations, and national's microwire speci?cations. the port consists of a transmit data line (txd), a receive data line (rxd), a chip select line ( cs), and a synchronous clock input (sclk). all memory locations and control functions on the minidx are accessed through this port. the microport may also be con?gured in serial bus mode where data is clocked into the connect memory in the same way as sti0 and sti1 are clocked into data memory. in serial microport mode, cs must be low to enable a microport access. sclk clocks the serial microport data in or out through rxd and txd, lsb ?rst. the txd output driver is tristated when it is inactive. this allows rxd and txd to be connected together for a single txd/rxd line as used in the intel mcs-51 microcontrollers. figure 3 shows a serial microport access cycle. a microport access cycle (microcycle) begins with a falling edge on cs. eight bits of data are clocked into rxd by the rising edge of sclk. two of these eight bits indicate whether the microcycle operation is a read or a write, the rest of the bits are used for addressing. these eight bits are de?ned as the command/ address byte (table 1). if the microcyle operation is a write, another eight bits are clocked figure 3 - serial microport timing d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 rxd txd sclk cs minimum delay between accesses equals 3.0 m sec. the mini dx: - latches received data in on the rising edge of sclk ? a ? a the falling edge of cs indicates that a command/address byte will be transmitted. subsequent byte is always data. ? subsequent write microcycles may flow without raising cs. cs must go high after a read microcycle. command/address data input/output command/address - outputs transmit data on the falling edge of sclk
iso-cmos MT8982 2-35 into rxd by the rising edges of the next eight sclk cycles. if the operation is a read, eight data bits are clocked from txd by the falling edges of the next eight sclk cycles. the rising edge of cs tristates txd after the last transmitted bit. successive write microcycles can take place while cs remains low, with each microcycle following the sequence of a command/address byte followed by a data byte. cs must go high after a read microcycle. note that a command/address byte must always follow the high to low transition on cs. when the mps input is pulled high and the cs input is pulled low, the microport is put into serial bus mode. pins rxd and sclk become csti0 and csti1, respectively, and are con?gured as 2048 kbit/ s serial streams with 32 channels each. the frame and timeslot boundaries are determined by f0i and c4. each channel on csti0 and csti1 is stored in the connect memory address corresponding to the link and channel number. the data memory and the connect memory cannot be read when the microport is in serial bus mode. device timing during each tdm timeslot, eight read or write operations occur internally in the MT8982. these are shown in figure 4. during the ?rst two bit periods, data received in the previous timeslot on the two input tdm streams is loaded into the data memory. bit periods 2 and 6 are serial microport access windows; data may be read from, or written to any accessible memory location. during bit periods 3 and 5, data is read from the connect memory for the next timeslot on links 0 and 1 respectively. the data memory locations which are addressed by the previous reads of the connect memory are accessed during bit periods 4 and 7. when the microport is in serial bus mode, bit periods 2 and 6 have a slightly different function. data from the previous timeslot of csti0 and csti1 respectively is written to the corresponding connect memory locations. the transfer of information from the input tdm streams to the output tdm streams results in a delay through the MT8982. this delay is dependent only on the combination of source and destination table 1. command address byte table 2. connect memory connection mode data byte bit name description 7 stream stream. this is the most signi?cant bit of the address for the memory location that is to be accessed. it corresponds to one of the tdm serial streams (0-1). 2-6 ch0-ch4 channel 0-4. these bits are the ?ve least signi?cant bits of the address for the memory location that is to be accessed. the binary value of these bits correspond to a tdm channel (0-31). 0-1 cmd0-cmd1 command select 0-1. these two bits de?ne the four command operations for the MT8982. the destination addressed by the command is de?ned in bits 2-7 of the command/address byte. cmd0-cmd1 0-0 read from connect memory. 0-1 write to connect memory and set connection mode. 1-0 read data memory. 1-1 write to connect memory and set message mode. bit name description 7 na unused. 6 ode output drive enable. when this bit is set, the addressed tdm channel is placed in tristate. when low, the output is enabled. 5 sti input stream. this bit de?nes the input tdm stream from which the output data is sourced (0-1). 0-4 sc0-sc4 source channel 0-4. the binary value of these bits de?nes the input channel from which the output data is sourced (0-31).
MT8982 iso-cmos 2-36 figure 4 - internal memory access windows channel 31 channel 0 c4 f0i microport mode serial port mode wr dm link 0 ch 31 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 wr dm link 1 ch 31 wr cm link 0 ch 31 rd dm link 1 ch 1 rd cm link 1 ch 1 rd dm link 0 ch 1 rd cm link 0 ch 1 wr cm link 1 ch 31 m p m p channels and is not dependent on the input and output streams. the delays are given in table 3. the maximum delay is one frame plus one channel; the minimum delay is two channels. table 3. input channel to output channel delay times the following delays apply to writing data to the connect memory in message mode. for stream 0, data must be written to a connect memory location at least one timeslot before the corresponding output channel or the output data will be delayed by one frame. for stream 1, data must be written at least two timeslots before the output channel or the output data will be delayed by one frame. device programming microport mode in serial microport mode, the MT8982 is programmed and read using microcycles which consist of a command/address byte followed by a data byte. the command/address byte is shown in table 1. bits 0 and 1 are the command bits (cmd0-1), and are used to indicate the type of microcycle access. the microcontroller can read the data memory, read or write the connect memory, and set per-channel message or connection mode. bits 2 to 6 of the command/address byte (ch0-ch4) correlate to a channel on a tdm stream (0-31). bit 7 (stream) correlates to stream 0 or stream 1. these bits address the corresponding data memory or connect memory location. the microcycle operations selected by the command/address byte are as follows: read connect memor y (cmd0-1: 0,0) bits 0 to 7 of the addressed connect memory location will be transmitted to the microcontroller in the following data byte. depending on what the last connect memory write mode was, the data transmitted could be a message byte or a connection mode data byte. input channel output channel delay n m = n, n+1 m- n + 32 channels n m > n+1 m- n channels n m < n 32- (n-m) channels
iso-cmos MT8982 2-37 wr ite connect memor y - set connection mode (cmd0-1: 0,1) the corresponding output channel to the addressed connect memory location is con?gured in connection mode. the connection mode data byte (table 2) will be received by the MT8982 in the following data byte. bits 0 to 4 (sc0-sc4) select the source input channel for switching to this output channel. bit 5 (sti) selects the input stream. bit 6 (ode) enables/ disables tristate for this channel. bit 7 is unused in connection mode. read data memor y (cmd0-1: 1,0) the contents of the addressed data memory location are transmitted to the microcontroller in the following data byte. wr ite connect memor y - set message mode (cmd0-1: 1,1) the corresponding output channel to the addressed connect memory location is con?gured in message mode. the following data byte will be received by the MT8982 and written to the address connect memory location. the data byte will be output directly to the corresponding output channel. the following example shows a typical programming sequence for the MT8982. a connection is to be made from stream 1 channel 6 to stream 0 channel 15: ? the microcontroller pulls cs low. ? the microcontroller transmits eight clock pulses to sclk and a command/address byte, hex 3e, to rxd. the command/address byte addresses output channel 15, stream 0, con?gures that channel as connection mode and identi?es the microcycle as a write to the connect memory. ? the microcontroller transmits another eight clock pulses to sclk and sends the connection mode data byte, hex 26, to rxd. the connection mode data byte addresses input channel 6, stream 1 in the data memory. note that at least two microseconds must occur between the two accesses. the connection is now complete. the microcontroller may now check that the connection is correct: ? the microcontroller transmits eight clock pulses to sclk and a command/address byte, hex 3c, to rxd. the command/address byte addresses output channel 15, stream 0 and identi?es the microcycle as a read from the connect memory. ? the microcontroller transmits another eight clock pulses to sclk. the MT8982 outputs the connect memory data, hex 26, on txd. at least two microseconds must occur between the two accesses to ensure that the minidx can clock out the data. ? cs goes high to terminate the session. this connection is only in one direction. to make a bidirectional connection the MT8982 must also be programmed to connect stream 0 channel 15 to stream 1 channel 6. serial bus mode when the microport is in serial bus mode the MT8982 is programmed via the two st-bus serial streams csti0 and csti1. each channel in these two streams is written directly into the corresponding address in the connect memory. the data written to the connect memory is always the connection mode data byte as described in table 2. to set up a connection, the connection mode data byte is transmitted to the MT8982 on the csti stream and channel number which is the same as the desired sto stream and channel number. as long as the device remains in serial bus mode, the connection mode data byte must be transmitted continuously, every frame, to maintain the connection. message mode is not available when the device is in serial bus mode. also, neither the connect memory nor the data memory can be read while the device is in serial bus mode. mitels mt8980, mt9080 and mt8920 devices can all be used as programmable parallel-to-st-bus serial interfaces for csti0 and csti1. initialization on power up the contents of the connect memory can be in any state. in order to prevent false programming of peripheral st-bus devices or false data transmission, ode should be kept low during power up. this will keep the two tdm outputs in high impedance until the MT8982 connect memory is programmed.
MT8982 iso-cmos 2-38 applications digital key telephone system figure 5 shows a block diagram of a digital key telephone system (dkts) implemented with the MT8982. this dkts can support up to 64 connections organized in any combination of subscriber lines or trunks. a very small system consisting of six lines and one trunk can very easily and economically be designed on one board. the MT8982 signi?cantly reduces the tracking and board space required for competitive switch matrices. distributed switching system the MT8982 can be used to distribute switching capability in a very large system. in figure 6 the MT8982 is shown with the microport in serial bus mode. this allows the central microprocessor to set up and tear down connections at the remote locations by programming the remote MT8982's through their csti pins. a microcontroller in each remote switch would not be required. primary rate serial controller figure 7 shows the MT8982 used in a primary rate serial control application. the MT8982 is used as the control interface from a microcontroller to mitels mh89760/790 t1 primary rate interfaces using the microcontrollers serial microport. the MT8982 of?oads signalling and trunk control functions from the central switch matrix leaving more capacity for switching. st-bus to gci conversion the MT8982 minidx may be used to provide a gateway between mitel's st-bus family of components and an architecture which utilizes the general circuit interface (gci) operating at 2048 kbit/s (figure 8). the MT8982 performs automatic adaptation of the different frame pulse signals. the master frame pulse to the MT8982 can be supplied either by the st-bus or the gci components. the MT8982 will then provide either a delayed or advanced frame pulse to the other components as shown in figures 9 and 10. when an st-bus component is supplying the master frame pulse ( f0i), the minidx will supply the output frame pulse ( f0o) delayed by ?ve channels. this ensures that frame integrity is maintained between the st-bus and gci components. when a gci component supplies the master frame pulse ( f0i), f0o is adv anced by ?ve channels. figure 8 shows a block diagram of a gci to st-bus conversion circuit. external inversion of the clock signal is required between the st-bus and gci components because the st-bus and gci master c4 clocks use different edges to mark bit boundaries. to program a connection between a st-bus channel and a gci channel, some channel conversion is necessary. figure 11 shows the relationship between the st-bus basic access frame and the gci basic access frame. because the MT8982 shifts the gci frame pulse (input or output) by ?ve channels, all of the gci channels must be incremented by ?ve to be correctly addressed by the figure 5 - digital key telephone system (dkts) mt8972 dnic mt8972 dnic mt8972 dnic MT8982 minidx mh88630/1 c.o. trunk to central of?ce microcontroller ? ? ? central dkts controller
iso-cmos MT8982 2-39 figure 6 - distributed switching system figure 7 - primary rate serial controller m p mt9080/85s large switch matrix MT8982 minidx subscriber interface 0 subscriber interface 32 subscriber interface 0 subscriber interface 32 small remote switch 1 small remote switch n ? ? ? ? ? ? ? ? MT8982 minidx large central switch & central control sti0 sti0 csti0 csti1 sti0 sto0 csti0 csti1 sti1 sto1 sti1 sto1 ? ? parallel m p interface serial m p interface mt8952 d-channel protocol controller MT8982 minidx mh89760/790 t1 trunk dsti dsto csti0 csti1 csto sto0 sto1 sti0 cdsto cdsti mt8980 switch matrix sto0 sti0
MT8982 iso-cmos 2-40 figure 8 - gci/st-bus interface pcm streams gci clk (4.096 mhz) gci frame pulse sto0 sti0 c4i f0i f0o sti1 sto1 sto sti c4i f0i MT8982 minidx mitel basic rate phone components st-bus frame pulse MT8982. therefore, to connect gci channel b1 to st-bus channel b1, the MT8982 must be programmed to connect channel 5 to channel 2. the ?ve channel offset ensures that all four basic rate channels will be switched together within one frame period, regardless which direction the data is being switched. the ?ve channel offset for gci channels is required even in gci to gci switching systems. for example, to switch gci channel b1 to gci channel b2, the MT8982 must be programmed to connect channel 5 to channel 6. figure 9 - st-bus/gci timing with st-bus as master figure 10 - st-bus/gci timing with gci as master figure 11 - switching gci and st-bus basic rate access channels channel 0 channel 4 channel 5 f0i c4i f0o channel 0 channel 4 channel 5 f0i c4i f0o st-bus gci ch0 ch1 ch2 ch3 d c b 1 b 2 m d and c/i - st-bus and minidx channels b 1 b 2 ch0(5) ch1(6) ch2(7) ch3(8) - gci (minidx) channels
iso-cmos MT8982 2-41 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . absolute maximum ratings * parameter symbol min max units 1 power supply voltage v dd -v ss v dd -v ss 6v 2 voltage on any pin v i v ss -0.3 v dd +0.3 v 3 current at any pin (other than supply) i o 100 ma 4 storage temperature t s -65 +150 c 5 package power dissipation p d 1000 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 operating temperature t op -40 +85 c 2 power supply v dd 4.5 5.5 v 3 input voltage v i v ss v dd v dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 operating supply voltage v dd 4.5 5.0 5.5 v 2 operating supply current i dd 2.0 ma outputs unloaded 3 static supply current i dds 100 m a all inputs =v dd 4 high level input v ih 2.0 v 5 low level input voltage v il 0.8 v 6 input leakage current i ih /i il 10.0 m av in =v ss or v dd 7 low level output voltage v ol 0.4 v i ol = 4.0 ma 8 high level output voltage v oh 2.4 v i oh = 2.0 ma 9 output low (sink) current i ol 4.0 ma v out =0.4 v 10 output high (source) current i oh 2.0 ma v out =2.4v, v dd =4.5v ac electrical characteristics ? - serial microport (see figure 12) - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 chip select setup time t cs 5ns 2 rxd input setup time t rs 40 ns 3 rxd input hold time t rh 0ns 4 txd output delay t td 80 ns c l =50pf, r l =1k w 5 txd output tristate delay t daz 140 ns c l =50pf, r l =1k w * 6 sclk pulse width high t ppwh 190 ns 7 sclk pulse width low t ppwl 190 ns 8 command/data byte delay time t cdbd 2 m s
MT8982 iso-cmos 2-42 figure 12 - serial microport timing figure 13 - tdm bus timing cs sclk rxd txd t cs t cdbd t ppwh t ppwl t rs t rh t td t td t daz bit 0 bit 7 bit 0 bit 7 f0i (st-bus) f0i c4i dsto0-1 dsti0-1 csti0-1 t fs t fh t sdaa t sdaz t sdza t fs t fh t ss t sh 10 cycles of c4i (gci)
iso-cmos MT8982 2-43 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . figure 14a - tdm bus timing - f0o/clock timing figure 14b - ode timing ac electrical characteristics ? - tdm bus (see figures 13 and 14a, 14b). voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 frame pulse input setup time t fs 10 ns 4 meg mode 2 frame pulse input hold time t fh 5 5 ns cycles 3 serial output delay; active to active t sdaa 100 ns c l =50pf 4 serial output delay; active to high z t sdaz 200 ns c l =50pf r l =1k w * 5 serial output delay; high z to active t sdza 150 ns c l =150pf 6 serial input setup time t ss 20 ns 7 serial input hold time t sh 10 ns 8 frame pulse output delay t fd 70 ns 9 ode low to serial out high z t saz 125 ns c l =50pf, r l =1k w * 10 ode high to serial out active t sza 50 ns c l =50pf, r l =1k w 11 c4 clock pulse width low t c4l 25 100 209 ns t c4 = 244 ns 12 c4 clock pulse width high t c4h 35 100 219 ns t c4 = 244 ns 13 c4 clock period t c4 150 244 ns f0o (st-bus) c4i f0o (gci) t fd t fd t c4 t c4l t c4h t fd t fd ode sto0-1 t saz t sza
MT8982 iso-cmos 2-44 notes:
package outlines plastic dual-in-line packages (pdip) - e suf?x note: controlling dimensions in parenthesis ( ) are in millimeters. dim 8-pin 16-pin 18-pin 20-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) a 2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) c 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) d 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) e 1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) l 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) e b 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) e c 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b e c general-8
package outlines plastic dual-in-line packages (pdip) - e suf?x dim 22-pin 24-pin 28-pin 40-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) a 2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) c 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) d 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) e 0.290 (7.37) .330 (8.38) e 1 0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 1 0.246 (6.25) 0.254 (6.45) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.400 bsc (10.16) 0.600 bsc (15.24) 0.600 bsc (15.24) 0.600 bsc (15.24) e a 0.300 bsc (7.62) e b 0.430 (10.92) l 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) a 15 15 15 15 e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b a shaded areas for 300 mil body width 24 pdip only
package outlines lead soic package - s suf?x notes: 1. controlling dimensions in parenthesis ( ) are in millimeters. 2. converted inch dimensions are not necessarily exact. dim 16-pin 18-pin 20-pin 24-pin 28-pin min max min max min max min max min max a 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) a 1 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) b 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.030 (0.51) 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.020 (0.51) c 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) d 0.398 (10.1) 0.413 (10.5) 0.447 (11.35) 0.4625 (11.75) 0.496 (12.60) 0.512 (13.00) 0.5985 (15.2) 0.614 (15.6) 0.697 (17.7) 0.7125 (18.1) e 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) e 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) h 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) l 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) pin 1 a 1 b e e a l h c notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) a & b maximum dimensions include allowable mold flash d l 4 mils (lead coplanarity) general-7
package outlines small shrink outline package (ssop) - n suf?x pin 1 a 1 b e d e a l h c a 2 dim 20-pin 24-pin 28-pin 48-pin min max min max min max min max a 0.079 (2) - 0.079 (2) 0.079 (2) 0.095 (2.41) 0.110 (2.79) a 1 0.002 (0.05) 0.002 (0.05) 0.002 (0.05) 0.008 (0.2) 0.016 (0.406) b 0.0087 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.2) 0.0135 (0.342) c 0.008 (0.21) 0.008 (0.21) 0.008 (0.21) 0.010 (0.25) d 0.27 (6.9) 0.295 (7.5) 0.31 (7.9) 0.33 (8.5) 0.39 (9.9) 0.42 (10.5) 0.62 (15.75) 0.63 (16.00) e 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.291 (7.39) 0.299 (7.59) e 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) a 2 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.089 (2.26) 0.099 (2.52) h 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.395 (10.03) 0.42 (10.67) l 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.02 (0.51) 0.04 (1.02) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) ref. jedec standard m0-150/m0118 for 48 pin 5) a & b maximum dimensions include allowable mold flash general-11
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